Testing of Dual Slope Integrator ASIC (DMILL chip)

The DMILL CDS chip

       This first approach is centered on the use of DMILL (an intrisically radhard process) and a complex  ASIC (aiming at optimized S/N ratio)
       J.F.Genat in collaboration with the LBL electronic group (H. von der Lippe and  C.Grace).

            design (schematics); realization (DMILL chip layout)

Test setup

setup (Rachids's)

Test results

  • first reports  report-1, report-2, report-3
  • 01/06/02 summary,

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     Etienne Barrelet     Last modified: June 23, 2004