R&D PROJECTS

Second generation Clamp & Sample ASIC

This ASIC will integrate the ADC (AMS 12 bit) with the dual gain clamp and sample functions of the first generation chip

Direct Illumination Calibration Experiment for SuperNovae

• Project passed first steps: Concept paper, LPNHE scientific council (report), Proposal submitted to CFHT, LPNHE CSP
• femtoAmmeter Asic submitted
  
• LED controller drawn
  

IN2P3 common platform

• Overview of previous status