ASICS
The
three ASICs presented below were developped to optimize the front-end
stage of low-noise detector readout, either for CCD and IR pixel
imagers in SNAP (Dual slope integrator and Clamp & sample), or for Cooled
large area photodiodes in SNDICE (femto-ammeter).A fourth new ASIC is being developped with LAL(Orsay), for CCD imager front-end in LSST (Dual Slope Integrator & Clamp & Sample)
Dual Slope Integrator (DMILL)
Layout of Dual Slope Integrator ASIC
- DSI Asic test reports
Clamp & Sample dual gain (AMS 0.35 μ)
Clamp&Sample ASIC low noise test setup
- Hardware description
- Understanding Asic non-conformities
- Commissioning Asic: linearity, cooling and radiation
- Results : General Report LPNHE 2004-11,
C.J.'s Thesis
- Hardware description,
pictures,
Femto-Ammeter amplifier (AMS 0.35 μ)
in box: CLAP housing (left), Asic (gilded), front electronics
- Results : ASIC test report LPNHE 2007-4