The three ASICs presented below were developped to optimize the front-end stage of low-noise detector readout, either for CCD and IR pixel imagers in SNAP (Dual slope integrator and Clamp & sample), or for  Cooled large area photodiodes in SNDICE (femto-ammeter).
A fourth new ASIC is being developped with LAL(Orsay), for CCD imager front-end in LSST (Dual Slope Integrator & Clamp & Sample)

Dual Slope Integrator  (DMILL)

ccd bench
      Layout of Dual Slope Integrator ASIC


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Clamp & Sample dual gain (AMS 0.35 μ)

IR bench
       Clamp&Sample ASIC low noise test setup

     aspic view

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Femto-Ammeter amplifier (AMS 0.35 μ)

IR bench 
        in box: CLAP housing (left), Asic (gilded), front electronics

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Etienne Barrelet
Last modified: July 14th  2007